A logic gate is an arrangement of electronically controlled switches used to proceed calculations in Boolean algebra. Logic gates can be constructed from relays, diodes, transistors and other elements. The logic gates constructed from the metal-oxide-semiconductor (MOS) transistors represent basic components of digital integrated circuits (ICs). The MOS logic gates are programmable and can perform different logic functions such as NOT, AND, OR, NAND, NOR and others.
FIG. 1 shows a circuit diagram of a complementary MOS (CMOS) inverter (or a logic gate) 10 for performing a NOT logic function according to a prior art disclosed by F. Wanlass in U.S. Pat. No. 3,356,858 (1967). The inverter 10 comprises a n-channel MOS transistor nT coupled to a low source voltage 12 (VSS) and a p-channel MOS transistor pT coupled to a high source voltage 14 (VDD). An input signal A applied to an input terminal 16 controls the nT and pT transistors. The inverter 10 performs the logic function NOT. An output signal Y at an output terminal 18 is an inversion of the input signal A (Y=A′). The CMOS inverter 10 found a broad application in digital ICs to perform the logic functions AND, OR, NAND, NOR and others. However the CMOS inverter 10 is volatile and loses its logic state when the power is off.
Alternatively, a magnetic tunnel junction (MTJ) is a nonvolatile magneto-resistive device (MRD) employing giant magneto-resistance (GMR) effect observed in a multilayer structure composed by at least two ferromagnetic layers separated by a thing oxide layer. When magnetizations of the ferromagnetic layers are parallel to each other, a tunneling resistance RP of the MTJ is low and is referred to as a logic state “0”. When the magnetizations of the ferromagnetic layers are anti-parallel, the resistance RAP of the MTJ is high and is referred to as a logic state “1”. In the MTJ one ferromagnetic layer, called a pinned or reference layer, has a fixed direction of the magnetization. The direction of the magnetization in the other layer that is called as a free or storage layer can be reversed from parallel to anti-parallel relatively to the direction of the magnetization in the pinned layer by applying an appropriate magnetic field or by running a spin polarized current through the MTJ in a direction perpendicular to a plane of the junction. The logic states “0” or “1” can be determined by comparing the resistance of the MTJ with a known reference resistance. The MTJ is a nonvolatile device. It doesn't lose its logic state when the power is off.
FIG. 2 shows a circuit diagram of a nonvolatile inverter 20 according to a prior art disclosed by R. Katti and T. Zhu in U.S. Pat. No. 7,339,818 (2008) and No. 8,004,882 (2011). The inverter 20 comprises a MTJ 22 that is coupled in series between two complimentary MOS transistors nT and pT. A logic state of the inverter 20 stores in the MTJ 22 and cannot be lost when the power is off. The MTJ 22 employs a spin polarized current for changing its logic state. Hence the logic state of the MTJ 22 can be controlled by a direction of the spin polarized current running through the junction during programming. To reverse the direction of the spin polarized current in the MTJ 22 the polarity of voltage sources 12 (VSS) and 14 (VDD) needs to be changed. A necessity to change the polarity of the voltages sources during an operation in the nonvolatile inverter 20 leads to several disadvantages.
For example, the CMOS inverter requires that a source terminal of the p-channel pT and n-channel nT transistors be connected to the high voltage source (VDD) and to the low voltage source (VSS), respectively. The opposite polarity of the voltage sources is not desirable since it leads to a substantial increase of power consumption by the inverter due to a power leakage in the transistors. Moreover the opposite polarity of the voltage sources might cause a reduction of a saturation current of the transistors nT and pT. This obstacle might prevent the magnetization reversal in the MTJ 22 of the nonvolatile inverter 20 hence it might prevent the MTJ 22 from memorizing the logic state of the CMOS logic circuit formed by the transistors.